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lt1950 1 1950fa wide input range: 3v to 25v programmable volt-second clamp output power levels from 25w to 500w auxiliary boost converter provides 10v gate drive from v in as low as 3v programmable operating frequency (100khz to 500khz) with one external resistor programmable slope compensation programmable leading edge blanking 2% internal 1.23v reference accurate shutdown pin threshold with programmable hysteresis 60ns current sense delay 2.5v auxiliary reference output synchronizable to an external clock up to 1.5 ? f osc current mode control small 16-pin ssop package telecom power supplies automotive power supplies portable electronic equipment isolated and nonisolated dc/dc converters single switch pwm controller with auxiliary boost converter , ltc and lt are registered trademarks of linear technology corporation. slope v ref boost r osc blank sync gnd fb v in v in2 v sec shdn gate i sense pgnd comp lt1950 1950 ta01a 0.1 f 249k 4.99k 4.7k 0.022 f 1 f 470k 18k 10v bias 100k v in mbrb20200 47 h 47 f v out 26v 5a 0.015 ? si7450 2.5v pa0581 efficiency vs load current load current (a) 0.5 efficiency (%) 95 90 85 80 75 70 4.5 1950 ta01b 1.5 2.5 3.5 5.5 v in = 48v v in = 36v v in = 72v 36v to 72v dc to 26v/5a (single switch) forward converter the lt ? 1950 is a wide input range, forward, boost, flyback and sepic controller that drives an n-channel power mosfet with few external components required. a resistor programmable duty cycle clamp can be used to generate a volt-second clamp for forward converter appli- cations. an internal boost switcher is available for creating a separate supply for the output gate driver, allowing 10v gate drive from input voltages as low as 3v. the lt1950s operating frequency can be set with an external resistor over a 100khz to 500khz range and a sync pin allows the part to be synchronized to an external clock. additional programmability exists for leading edge blanking and slope compensation. a fast current sense comparator achieves 60ns current sense delay and the error amplifier is a true voltage mode error amplifier, allowing a wide range of compensation networks. an accurate shutdown pin with programmable hysteresis is available for undervoltage lockout and shut- down. the lt1950 is available in a small 16-pin ssop package. applicatio s u features descriptio u typical applicatio u
lt1950 2 1950fa order part number gn part marking t jmax = 125 c, ja = 110 c/w, jc (pin 8) = 30 c/w 1950e 1950i lt1950egn lt1950ign absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. comp = open, fb = 1.4v, r osc = 249k, sync = 0v, slope = open, v ref = 0.1 f, shdn = v in , blank = 0v, i sense = 0v, v in2 = 15v, gate = 1nf, boost = open, v in = 15v, v sec = 0v, unless otherwise specified. consult ltc marketing for parts specified with wider operating temperature ranges. top view gn package 16-lead narrow plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 comp fb r osc sync slope v ref shdn gnd v sec v in boost pgnd gate v in2 i sense blank parameter conditions min typ max units pwm controller operating input voltage i vref = 0 a 3.0 25 v minimum start-up voltage i vref = 0 a 2.6 3.0 v v in quiescent current i vref = 0 a, fb = 1v, i sense = 0.2v 2.3 3.0 ma v in shutdown current shdn = 0v 5 20 a shutdown threshold 3v < v in < 25v 1.261 1.32 1.379 v shutdown pin current shdn = 70mv above threshold C7 C10 C13 a shutdown pin current hysteresis shdn = 100mv below threshold 4 7 10 a v in2 quiescent current i(v ref ) = 0 a, fb = 1v, i sense = 0.2v 1.7 2.5 ma v in2 shutdown current shdn = 0v, v in2 = 2.7v (boost diode from v in = 3v) 500 700 a v ref (external output) output voltage i vref = 0 a 2.425 2.500 2.575 v line regulation i vref = 0 a, 3v < v in < 25v 1 5 mv load regulation 0 a < i vref < 2.5ma 1 5 mv oscillator frequency: f osc r osc = 249k, fb = 1v 170 200 230 khz minimum programmable f osc r osc = 499k 85 100 115 khz maximum programmable f osc r osc = 90.9k 440 500 560 khz sync input resistance 20 k ? sync switching threshold 1.5 2.2 v sync frequency/f osc (r osc = 249k, f osc =200khz), fb = 1v (note 7) 1.25 1.5 f osc line reg 3v < v in < 25v 0.05 0.15 %/v 9.5v < v in2 < 25v 0.05 0.25 %/v v rosc 1v boost ....................................................... C0.3v to 35v v in , v in2 , shdn ......................................... C0.3v to 25v fb, sync, v sec ........................................... C0.3v to 6v comp, blank .......................................... C0.3v to 3.5v slope ...................................................... C0.3v to 2.5v i sense ......................................................... C0.3v to 1v r osc .................................................................... C50 a v ref .................................................................... C10ma operating junction temperature range lt1950egn/lt1950ign (notes 2, 5) ... C 40 c to 125 c storage temperature range ..................C65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c
lt1950 3 1950fa electrical characteristics parameter conditions min typ max units the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. comp = open, fb = 1.4v, r osc = 249k, sync = 0v, slope = open, v ref = 0.1 f, shdn = v in , blank = 0v, i sense = 0v, v in2 = 15v, gate = 1nf, boost = open, v in = 15v, v sec = 0v, unless otherwise specified. error amplifier fb reference voltage 3v < v in < 25v, v ol + 0.2v < comp < v oh C 0.2 1.205 1.230 1.254 v fb input bias current fb = fb reference voltage C75 C200 na open loop voltage gain v ol + 0.2v < comp < v oh C 0.2 65 85 db unity gain bandwidth (note 6) 3 mhz comp source current fb = 1v, comp = 1.6v C0.3 C1.1 C1.8 ma comp sink current fb = 1.4v, comp = 1.6v 8 13 ma comp high level: v oh fb = 1v, i comp = C 250 a 2.5 v comp active threshold start of gate switching (duty cycle > 0%) 1.0 v comp low level: v ol fb = 1.4v, i comp = 250 a 0.15 v current sense i sense maximum threshold duty cycle < 10%, comp = v oh 90 100 110 mv i sense input bias current comp = 2.5v, i sense = i sense max threshold C125 C170 C250 a default blanking time fb = 1v, comp = 2v, i sense = 75mv 110 ns adjustable blanking time fb = 1v, comp = 2v, i sense = 75mv 290 ns blank = 75k to ground blanking override voltageC blank = open, comp = 2.5v (note 4) 15 25 40 mv i sense maximum threshold turn-off delay to gate comp = 2v 60 ns slope compensation (note 4) i sense max threshold (dc < 10%) C (dc = 80%) (note 4) default, r slope = 14 mv 2x default, r slope = 8k 28 mv 3x default, r slope = 3.3k 42 mv internal switcher boost switch i limit v in2 = 8v, 3v < v in < 10v 70 125 180 ma boost switch off time v in2 = 8v, 3v < v in < 10v 250 500 1000 ns v in2 : boost disable 3v < v in < 10v 9.5 11.0 11.75 v v in2 : boost disable hysteresis 3v < v in < 10v C1.0 v v in2 : gate enable 3v < v in < 10v, fb = 1v (note 4) 7.0 8.2 9.27 v v in2 : gate enable hysteresis 3v < v in < 10v, fb = 1v (note 4) C0.6 v gate driver output gate rise time fb = 1v, v in2 = 12v, c l = 1nf (notes 3, 6) 50 ns gate fall time fb = 1v, v in2 = 12v, c l = 1nf (notes 3, 6) 30 ns gate clamp voltage i gate = 0 a, comp = 2.5v, fb = 6v 11.5 13 14.5 v gate low level i gate = 20ma 0.25 0.4 v i gate = 200ma 1.2 1.75 v gate high level i gate = C20ma, v in2 = 12v, comp = 2.5v, fb = 6v 10 v i gate = C200ma, v in2 = 12v, comp = 2.5v, fb = 6v 9.75 v maximum duty cycle fb = 1v, f osc = 200khz 90 95 97 %
lt1950 4 1950fa temperature ( c) C50 fb voltage (v) 1.26 1.25 1.24 1.23 1.22 1.21 1.20 25 75 1950 g01 C25 0 50 100 125 temperature ( c) C50 frequency (khz) 1950 ? g02 0 50 100 240 230 220 210 200 190 180 170 160 C25 25 75 125 temperature ( c) C50 v in shutdown i q ( a) 1950 ? g03 0 50 100 16 14 12 10 8 6 4 2 0 C25 25 75 125 shdn = 0v temperature ( c) C50 shutdown threshold (v) 1950 ? g04 0 50 100 1.45 1.40 1.35 1.30 1.25 1.20 C25 25 75 125 temperature ( c) C50 maximum i sense threshold (mv) 125 120 115 110 105 100 95 90 85 80 75 0 50 75 1950 g05 C25 25 100 125 i sense current ( a) 270 250 230 210 190 170 150 130 110 90 temperature ( c) C50 0 50 75 1950 g06 C25 25 100 125 parameter conditions min typ max units maximum duty cycle clamp v sec = 1.4v, fb = 1v, comp = v oh 63 75 87 % v sec input bias current 0v < v sec < 2.8v C0.3 C1.0 a note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the lt1950egn is guaranteed to meet performance specifications from 0 c to 125 c operating junction temperature. specifications over the C40 c to 125 c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt1950ign is guaranteed over the full C40 c to 125 c operating junction temperature range. note 3: rise and fall times are between 10% and 90% levels. fb voltage vs temperature switching frequency vs temperature v in shutdown i q vs temperature shutdown threshold vs temperature maximum i sense threshold vs temperature i sense pin current vs temperature electrical characteristics typical perfor a ce characteristics uw note 4: guaranteed by correlation to static test. note 5: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125 c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 6: guaranteed but not tested. note 7: maximum recommended sync frequency = 500khz. the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. comp = open, fb = 1.4v, r osc = 249k, sync = 0v, slope = open, v ref = 0.1 f, shdn = v in , blank = 0v, i sense = 0v, v in2 = 15v, gate = 1nf, boost = open, v in = 15v, v sec = 0v, unless otherwise specified.
lt1950 5 1950fa temperature ( c) C50 shdn current hysteresis ( a) 100 1950 g11 050 11 10 9 8 7 6 5 4 3 C25 25 75 125 gate capacitance (pf) 0 gate rise/fall time (ns) 125 100 75 50 25 0 4000 1950 g12 1000 2000 3000 5000 t r t f temperature ( c) C50 minimum v in start-up voltage (v) 100 1950 g08 050 3.00 2.75 2.50 2.25 2.00 C25 25 75 125 temperature ( c) C50 blank override threshold Ci sense maximum threshold (mv) 40 35 30 25 20 15 10 25 75 1950 g07 C25 0 50 100 125 temperature ( c) C50 v in i q (ma) 100 1950 g09 050 3.1 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 C25 25 75 125 14 12 10 8 6 4 2 0 shdn input current*(C1) ( a) temperature ( c) C50 25 75 1950 g10 C25 0 50 100 125 shdn = shdn threshold + 70mv shdn = shdn threshold C 100mv v in2 gate enable (v) 9.2 8.7 8.2 7.7 7.2 temperature ( c) C50 25 75 1950 g13 C25 0 50 100 125 gate disable gate enable hysteresis temperature ( c) C50 v in2 boost disable (v) 1950 g14 0 50 100 13.0 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 C25 25 75 125 boost disable boost re-enable hysteresis boost switch i limit (ma) 250 200 150 100 50 temperature ( c) C50 25 75 1950 g15 C25 0 50 100 125 t a = 25 c blank override threshold i sense maximum threshold vs temperature minimum v in start-up voltage vs temperature (v in2 boosted) v in i q vs temperature shdn input current *(?) vs temperature shdn current hysteresis vs temperature gate rise/fall time vs gate capacitance v in2 : boost disable vs temperature boost switch i limit vs temperature v in2 : gate enable vs temperature typical perfor a ce characteristics uw
lt1950 6 1950fa comp (pin 1): the comp pin is the output of the error amplifier. the error amplifier is a true op amp which allows the use of an rc network to be connected between the comp and fb pins to compensate the feedback loop for optimum transient response. the peak switch current in the external mosfet will be proportional to the voltage on the comp pin. typical operating voltage range for this pin is 1v to 2.5v. fb (pin 2): the fb pin is the inverting input to the error amplifier. the output voltage is set with a resistor divider. the error amplifier adjusts the peak switch current to maintain the fb pin voltage at the value of the internal reference voltage of 1.23v. r osc (pin 3): a resistor from the r osc pin to ground programs the operating frequency of the lt1950. operat- ing frequency range is 100khz to 500khz. nominal voltage on the r osc pin is 1v. sync (pin 4): the sync pin is used to synchronize the internal oscillator to an external clock signal. the pin is directly logic compatible and can be driven with any signal with a duty cycle of 10% to 90%. if the sync function is not used the pin can be left open circuit or connected to ground. typical perfor a ce characteristics uw uu u pi fu ctio s slope (pin 5): the slope pin is used to adjust the amount of slope compensation. leaving the pin open circuit results in a default level of slope compensation. the amount of slope compensation can be adjusted above this default level by connecting a resistor from the slope pin to the v ref pin. v ref (pin 6): the v ref pin is the output of an internal 2.5v reference. this pin is capable of sourcing up to 2.5ma for external use. it is recommended that the v ref pin is bypassed to ground with a 0.1 f ceramic capacitor. shdn (pin 7): the shdn pin is used to put the device into a low power shutdown state. in shutdown the v in supply current drops to 5 a. the shdn pin has an accurate threshold of 1.32v which can be used to program an undervoltage lockout threshold. input current levels on the shdn pin can be used to program hysteresis into the undervoltage lockout levels. gnd (pin 8): the gnd pin is the analog ground for the internal circuitry of the lt1950. sensitive circuitry such as the feedback divider, frequency setting resistor, reference bypass capacitor should be tied directly to this pin. see the applications information section for recommendations on ground connections. boost switch off time vs temperature maximum duty cycle vs v sec voltage gate clamp voltage vs temperature v sec voltage (v) maximum duty cycle (%) 100 90 80 70 60 50 40 30 1950 g17 0.8 1.2 1.6 2.0 2.4 2.8 3.2 temperature ( c) C50 gate clamp voltage (v) 100 1950 g18 050 16 15 14 13 12 11 10 C25 25 75 125 max duty cycle = (105/v sec )% 1.25v < v sec < 2.8v t a = 25 c boost switch off time (ns) 700 600 500 400 300 temperature ( c) C50 25 75 1950 g16 C25 0 50 100 125
lt1950 7 1950fa blank (pin 9): the blank pin is used to adjust the leading edge blanking period of the current sense amplifier during fet turn-on. shorting the blank pin to ground provides a default blanking period of approximately 110ns. a resistor from the blank pin to ground increases the blanking period up to 290ns for r blank = 75k. i sense (pin 10): the i sense pin is the current sense input for the control loop. connect this pin to the sense resistor in the source of the external power mosfet. v in2 (pin 11): the v in2 pin is the supply pin for the mosfet gate drive circuit. power can be supplied to this pin by an external supply such as v in , and must exceed 8v (the undervoltage lockout threshold for the gate driver supply). for low v in supply voltages an internal boost regulator can be used to generate as much as 11v at the v in2 pin. this allows the lt1950 to run with v in supply voltages down to 3v while still supplying enough gate drive for standard level mosfets. gate (pin 12): the gate pin is the output of a high current gate drive circuit used to drive an external mosfet. the output is actively clamped to a max voltage of 13v if v in2 is supplied by a high voltage. pgnd (pin 13): this is the ground connection for the high current gate driver stage. see the applications informa- tion section for recommendations on ground connec- tions. uu u pi fu ctio s boost (pin 14): the boost pin is the npn collector output of the internal boost converter which can be used to generate an 11v supply for the mosfet gate driver circuit. the boost converter runs with a fixed off-time of 0.5 s and a current limit of 125ma. the converter runs until the v in2 voltage exceeds 11v and then turns off until the v in2 voltage drops below 10v. if the v in2 voltage is supplied externally, the boost pin should be shorted to ground or left open. v in (pin 15): the v in pin is the main supply pin for the lt1950. this pin must be closely bypassed to ground. if v in2 is generated using the boost pin then the lt1950 will be fully functional, internal v ref will be active and the gate output will be enabled with a v in voltage as low as 3v. an internal undervoltage lockout threshold exists at ap- proximately 2.6v on the v in pin. undervoltage lockout voltages greater than 3v can be programmed using a voltage divider on the shdn pin. v sec (pin 16): the v sec pin is used to program the maximum duty cycle of the gate driver circuit. the maxi- mum duty cycle will be equal to (105/v sec )% for v sec between 1.4v and 2.8v. this is a useful function to limit the flyback voltage in a forward converter. if the maximum duty cycle function is not used then the v sec pin should be tied to ground.
lt1950 8 1950fa the lt1950 is a constant frequency, current mode con- troller for dc/dc forward, boost, flyback and sepic con- verter applications. the block diagram in figure 1 shows all of the key functions of the ic. in normal operation, a v in voltage as low as 3v allows an internal switcher at the boost pin to generate a separate block diagra w operatio u figure 1. lt1950 block diagram C + C + C + C + C + C + v ref = internal + external supply v in2 2.5v (source 2.5ma externally) 1.23v (v in ) (2.6v) u/v lockout (v in2 ) (8v) u/v lockout (100-500)khz (105/v sec )% osc (typical 200khz) 7 15 16 14 12 13 11 6 4 3 5 10 8 1 9 2 shdn sync r osc slope 1.32v 1.23v max dc clamp slope comp ramp s q r blanking fb comp gnd blank v ref v in v sec boost v in2 switching preregulator fixed off time (125ma current limit) pgnd disable C + current sense cmp blanking override cmp gate pgnd i sense 1a driver 13v enable 11v 8v 1950 bd 3 a C + error amplifier voltage gain = 85db 125mv 0mv C >100mv 11v supply at v in2 using a small surface mount external inductor, diode and capacitor. since v in2 supplies the output driver of the ic, this architecture achieves high gate drive for an external n-channel power mosfet even though v in voltage is very low. high gate drive capability reduces mosfet r ds(on) for improved efficiency,
lt1950 9 1950fa increases the range of mosfets that can be selected and allows applications requiring high gate drive with a large swing in v in voltage. when v in2 exceeds 8v, the gate output driver is enabled. the gate switches between 0v and v in2 at a constant frequency set by a resistor from the r osc pin to ground. when v in2 reaches 11v, the internal switcher at the boost pin is disabled to save power and only re-enabled when v in2 drops below 10v. the internal boost switcher runs in burst mode operation, asynchro- nous to the main oscillator. if low v in operation with high gate drive is not required, the boost pin is left open and the v in2 pin shorted to v in . with v in2 shorted to v in the minimum operational v in voltage will increase from 3v to 8v (required at v in2 to enable the gate output driver). for gate turn on, a pwm latch is set at the start of each main oscillator cycle. for gate turn off, the pwm latch is reset when either the current sense comparator is tripped, the maximum duty cycle is reached, or the blank override threshold is exceeded. a resistor divider from the applications output voltage generates a voltage at the fb pin that is compared to the internal 1.23v reference by the error amplifier. the error amplifier output (comp) defines the input threshold (i sense ) of the current sense comparator. maximum i sense voltage is clamped to 100mv. by connecting i sense to a sense resistor in series with the source of the external mosfet, the peak switch current is controlled by comp. an increase in output load current causing the output voltage to fall, will cause comp to rise, increasing i sense threshold, increasing the current delivered to the output. this current mode technique means that the error ampli- fier commands current to be delivered to the output rather than voltage. this makes frequency compensation easier and provides faster loop response to output load tran- sients. the current mode architecture requires slope compensa- tion to be added to the current sensing loop to prevent subharmonic oscillations which can occur for duty cycles above 50%. unlike most current mode converters which have a slope compensation ramp that is fixed internally, placing a constraint on inductor value and operating frequency, the lt1950 has externally adjustable slope operatio u compensation. a default level of slope compensation is achieved with the slope pin open. increased slope com- pensation can be programmed by reducing the value of resistance inserted between the slope pin and v ref pin. a sync pin allows the lt1950 main oscillator to be synchronized to an external clock . to avoid loss of slope compensation during synchronization, the free running main oscillator frequency should be programmed to ap- proximately 80% of the external clock frequency. the lt1950 can be placed into shutdown mode when the shdn pin drops below an accurate 1.32v threshold. this threshold can be used to program undervoltage lockout (uvlo) at v in for current limited or high source resistance supplies. shdn pin current hysteresis also exists to allow external programming of uvlo voltage hysteresis. when v in and v in2 exceed internally set uvlo thresholds of 2.6v and 6.8v, the v ref output becomes active. the v ref output is a 2.5v reference supplying the majority of lt1950 control circuitry and capable of sourcing up to 2.5ma for external use. to prevent noise in the system causing premature turn off of the external mosfet the lt1950 has leading edge blanking. this means the current sense comparator out- put is ignored during mosfet turn on and for an extended period after turn on. the extended blanking period is adjusted by inserting a resistor from the blank pin to ground. a short to ground defines a minimum default blanking period. increased resistance from the blank pin to ground will increase blanking duration. fault conditions causing i sense to exceed 125mv will override blanking and reduce the i sense to gate delay to 60ns. for applications requiring maximum duty cycle clamping, the v sec pin reduces duty cycle for increased voltage on the pin. the v sec pin provides a volt-second clamp critical in forward converter applications. maximum duty cycle follows (105/v sec )% for v sec volt- ages between 1.4v to 2.8v. if unused, the v sec pin should be shorted to ground, leaving the natural maximum duty cycle of the part to be typically 95% for 200khz operation.
lt1950 10 1950fa applicatio s i for atio wu u u lt1950 input supplies, v ref output and gate enable v in is the main input supply for the lt1950. v in2 is the input supply for the lt1950 output driver. v in2 can be provided by shorting the v in2 pin to the v in pin or by generating v in2 using the boost pin. waveforms of v in , v in2 , v ref and gate switching are shown in figures 2 and 3. figure 2 represents low v in operation with v in2 gener- ated using the b00st pin. figure 3 represents v in = v in2 operation with the boost pin open circuit or shorted to ground. low v in operation the lt1950 can be configured to provide a minimum of 10v gate drive for an external n-channel mosfet from v in voltages as low as 3v, if the boost pin is used to generate a second supply at the v in2 pin (see figure 2 and applications information generating v in2 supply using boost pin). the advantage of this configuration is that a lower r ds(on) is achieved for the external n-channel mosfet, improving efficiency, versus a controller run- ning at 3v input without boosted gate drive. in addition, typical controllers running at low input voltages have the limitation of only being able to use logic level mosfets. the lt1950 allows a greater range of usable mosfets. this versatility allows optimization of the overall power supply performance and allows applications which would otherwise not be possible without a more complex topol- ogy. figure 2 shows that for v in above 2v, the internal switcher at the boost pin is enabled. this switch gener- ates the v in2 supply. as v in2 ramps up above the undervoltage lockout threshold of 6.8v the 2.5v reference v ref becomes active and powers up internal control circuitry. when v in2 exceeds approximately 8v, the gate driver is enabled. v in2 is regulated between 10v and 11v, providing a supply to the lt1950 output driver to ensure a minimum of 10v drive at the gate pin. figure 2. low v in operation figure 3. v in = v in2 operation 12 8 4 0 v in 50 s/div boost v in2 v in lt1950 l1 d1 c1 min 3v 4 3 2 1 0 v ref 1950 f02 gate v in2 boost v in2 10.2 8.5 6.8 5.1 3.4 5.0 2.5 0 10 5 0 v in = v in2 v ref gate 10 s/div boost v in2 v in lt1950 typical start-up input >8.2v c1 * *boost pin can be left open or shorted to ground 1950 f03 boost v in2 v in = v in2 operation if low v in operation is not required below approximately 8v on v in the lt1950 can be configured to run without the use of the boost pin by shorting the v in2 pin to the v in pin. figure 3 shows that both v in and v in2 must now exceed 6.8v to activate the 2.5v v ref output and must exceed approximately 8v to enable the output driver (gate pin).
lt1950 11 1950fa applicatio s i for atio wu u u shutdown and undervoltage lockout figure 4 shows how to program undervoltage lockout (uvlo) for the v in supply. typically, uvlo is used in situations where the input supply is current limited, or has a relatively high source resistance. a switching regulator draws constant power from the source, hence source current increases as source voltage drops. this looks like a negative load resistance to the source and can cause the source to current limit or latch low under low source voltage conditions. an internally set undervoltage lockout (uvlo) threshold prevents the regulator from operating at source voltages where these problems might occur. an internal comparator will force the part into shutdown below the minimum v in of 2.6v. this feature can be used to prevent excessive discharge of battery-operated sys- tems. alternatively, uvlo threshold is adjustable. the shutdown threshold voltage of the shdn pin is 1.32v. forcing the shdn pin below this 1.32v threshold causes v ref to be disabled and stops switching at the gate pin. if the shdn pin is left open circuit, a permanent 3 a flows out of the pin to ensure that the pin defaults high to allow normal operation. voltages above the 1.32v threshold cause an extra 7 a to be sourced out of the pin, providing current hysteresis. this can be used to set voltage hyster- esis of the uvlo threshold using the following equations: r vv a r v vv r a hl h 1 7 2 132 132 1 3 = = + C . (C. ) v h = turn on threshold v l = turn off threshold example: switching should not start until the input is above 11v and is to stop if the input falls below 9v. v h = 11v v l = 9v r vv a k r v vv k a k 1 11 9 7 286 2 132 11 1 32 286 3 36 = = = + = C . (C.) keep the connections from the resistors to the shdn pin short and make sure that the interplane or surface capaci- tance to the switching nodes are minimized. if high resis- tance values are used, the shdn pin should be bypassed with a 1nf capacitor to prevent coupling problems from the switch node. figure 4. undervoltage lockout 3 a 7 a 1.32v gnd v ref v in r1 r2 c1 + 1950 f04 lt1950 generating v in2 supply using boost pin the lt1950s boost pin is used to provide a boosted 11v supply at the v in2 pin for v in voltages as low as 3v. since v in2 supplies the output driver for the gate pin of the ic, it is advantageous to generate a boosted v in2 . this architecture achieves high gate drive for an external
lt1950 12 1950fa n-channel power mosfet even though v in voltage is very low. high gate drive voltage reduces mosfet r ds(on) , improves efficiency and increases the range of mosfets that can be selected. a small switching regulator at the boost pin, with fixed current limit and fixed off time, generates the v in2 supply. with an external inductor connected between the boost pin and v in (see figure 5), the boost pin will draw current until approximately 125ma is reached, turn off for 0.5 s and then turn back on. the cycle is repeated for as long as the switcher is enabled. by using a diode connected from boost to v in2 and a capacitor from v in2 to ground, energy from the external inductor is transferred to the v in2 capacitor during the off- time of the internal switcher. an auxiliary boost converter is realized providing a supply to the v in2 pin. the typical inductor current, v in2 voltage and boost pin voltage waveforms are shown in figure 5. when v in2 reaches 11v, the internal switcher is disabled. since v in2 supplies the output driver of the lt1950, switching at the gate pin will eventually discharge the v in2 capacitor until v in2 reaches a lower level of approximately 10v. at this level the internal switcher is re-enabled and switches until v in2 returns to applicatio s i for atio wu u u figure 6. oscillator frequency (f osc ) vs r osc r osc (k ? ) 50 frequency (khz) 400 450 500 1950 f06 100 150 250 200 300 350 500 450 400 350 300 250 200 150 100 11v. this hysteretic (burst mode) operation for the inter- nal switcher minimizes power dissipation from v in . the v ref output is a 2.5v reference supplying most of the lt1950 control circuitry. it is available for external use with maximum current capability of 2.5ma. the pin should be bypassed to ground using a 0.1 f capacitor. internal undervoltage lockout thresholds for v in and v in2 of ap- proximately 2.6v and 6.8v respectively must be exceeded before v ref becomes active. programming oscillator frequency the oscillator frequency of the lt1950 is programmed using an external resistor connected between the r osc pin and ground. figure 6 shows typical f osc vs r osc resistor values. the lt1950 is programmable for a free-running oscillator frequency in the range of 100khz to 500khz. stray capacitance and potential noise pickup on the r osc pin should be minimized by placing the r osc resistor as close as possible to the r osc pin and keeping the area of the r osc node as small as possible. the ground side of the r osc resistor should be returned directly to the gnd (analog ground) pin. figure 5. v in2 generation using the boost pin boost v in2 v in lt1950 l1 d1 c1 min 3v 5 s/div 12 10 0.25 0 0.25 0 15 0 (v) (v) (a) (a) 1950 f05 boost v in2 i d1 i l1 boost v in2
lt1950 13 1950fa synchronizing the sync pin is used to synchronize the lt1950 main oscillator to an external clock. the sync pin can be driven directly from a logic level output, requiring less than 0.8v for a logic level low and greater than 2.2v for a logic level high. duty cycle must be between 10% and 90%. when synchronizing the part, slope compensation will be reduced by approximately sync f/f osc . if the reduction of slope compensation affects performance, r slope can be reduced to increase slope compensation and reestablish correct operation. if unused, the pin is left open or shorted to ground. if left open, be aware that the internal pin resistance is 20k and board layout should be checked to avoid noise coupling to the pin. slope compensation programmability the lt1950 allows its default level of slope compensation to be easily increased by use of a single resistor connected between the slope pin and the v ref pin. the ability to adjust slope compensation allows the designer to tailor his application for a wider inductor value range as well as to optimize the loop bandwidth. a resistor, r slope , con- nected between the slope pin and v ref increases the lt1950 slope compensation from its default level to as high as 3x of default. the curves in figure 7 show the typical i sense maximum threshold vs duty cycle for vari- ous values of r slope . it can be seen that slope compensa- tion subtracts from the maximum i sense threshold as duty cycle increases from 0%. for example, with r slope open, i sense max threshold is 100mv at low duty cycle, but falls to approximately 86mv at 80% duty cycle. this must be accounted for when designing a converter to operate up to a maximum load current and over a given duty cycle range. the application and inductor value will define the minimum amount of slope compensation. refer to the applicatio s i for atio wu u u electrical characteristics for 1x, 2x and 3x default slope compensation vs r slope . requirement in current mode converters/advantage of adjustability the lt1950 uses a current mode architecture to provide fast response to load transients and to ease frequency compensation requirements. current mode switching regu- lators which operate with duty cycles above 50% and have continuous inductor current, must add slope compensa- tion to their current sensing loop to prevent subharmonic oscillations. (for more information on slope compensa- tion see application note 19). typical current mode switch- ing regulators have a fixed internal slope compensation. this can place constraints on the value of the inductor. if too large an inductor is used, the fixed internal slope compensation will be greater than needed, causing opera- tion to approach voltage mode. if too small an inductor is used, the fixed internal slope compensation will be too small, resulting in subharmonic oscillations. the lt1950 increases the range of usable inductor values by allowing slope compensation to be adjusted externally. figure 7. i sense maximum threshold vs duty cycle duty cycle (%) 0 i sense max threshold (mv) 1950 f07 20 60 80 100 90 80 70 60 50 40 30 20 40 100 r slope = open r slope = 8k r slope = 3.3k
lt1950 14 1950fa applicatio s i for atio wu u u programming leading edge blank time for pwm controllers driving external mosfets, noise can be generated during gate rise time due to various para- sitic effects. this noise can disturb the input to the current sense comparator (i sense ) and cause premature turn-off of the external mosfet. the lt1950 provides program- mable leading edge blanking of the current sense com- parator to avoid this effect. blanking is provided in 2 phases: the first phase is during gate rise time. gate rise times vary depending on mosfet type. for this reason the lt1950 automatically blanks the current comparator output until the leading edge of the gate is detected. this occurs when the gate voltage has risen within 0.5v of the output driver supply (v in2 ) or has reached its clamp level of 13v. the second phase of blanking starts immediately after leading edge has been detected. this phase is programmable using a resistor (r blank ) from the blank pin to ground. typical values for this portion of the blanking period are 110ns at r blank = 0 ? up to 290ns at r blank = 75k. figure 8 shows blanking vs r blank . blanking duration can be approxi- mated as: blanking extended r k ns blank () ? =+ ? ? ? ? ? ? 110 60 25 figure 8. blanking timing diagram 1950 f04 r blank = 0 ? 0 ? < r blank < = 75k 60ns (automatic) leading edge blanking (default) extended blanking (programmable) extended blanking current sense delay gate blanking 0 xns (x + 110)ns [x + 110 + (60 ? r blank /25k)]ns programming volt-second clamp the v sec pin is used to provide an adaptive maximum duty cycle clamp for sophisticated control of the simplest forward converter topology (single primary-side switch). this adaptive maximum duty cycle clamp allows the use of the smallest transformers, mosfets and output rectifiers by addressing the biggest concern in single switch for- ward converter topologies - transformer reset. the sec- tion application circuits-forward converter applications covers transformer reset requirements and highlights the advantages of the lt1950 adaptive maximum duty cycle clamp. the programmable maximum duty cycle clamp is controlled by the voltage on the v sec pin. as voltage on the v sec pin increases within a specified range, maximum duty cycle decreases. by deriving v sec pin voltage from the system input supply, a volt-second clamp is realized. maximum gate output duty cycle follows a 1/x relation- ship given by (105/v sec )%. (see maximum duty cycle vs v sec voltage graph in the typical performance character- istics section). for example, if the minimum input supply for a forward converter application is 36v, the v sec pin can be programmed with a maximum duty cycle of 75% at 1.4v. a movement of input voltage to 72v will lift the v sec pin to 2.8v, resulting in a maximum duty cycle of 37.5%. as the section on forward converter applications will show, transformer reset requirements are met with the
lt1950 15 1950fa applicatio s i for atio wu u u ability of the v sec pin to follow input voltage and control maximum switch duty cycle. forward converter applications the lt1950 provides sophisticated control of the simplest forward converter topology (single primary switch, see q1 figure 11). a significant problem in a single switch for- ward converter topology is transformer reset. optimum transformer utilization requires maximum duty cycles. unfortunately as duty cycles increase the transformer reset time decreases and reset voltages increase. this increases the voltage requirements and stress on both transformer and switch. the lt1950 incorporates an adaptive maximum duty cycle clamp which controls maxi- mum switch duty cycle based on system input voltage. the adaptive clamp allows the converter to operate at up to 75% duty cycle, allowing 25% of the switching period for resetting the transformer. this results in greater utilization of mosfet, transformer and output rectifier components. the v sec pin can be programmed from system input to adaptively control maximum duty cycle (see applications information programming volt-sec- ond clamp and the maximum duty cycle vs v sec voltage graph in the typical performance characteristics section). figure 9. lt1950-based synchronous forward converter efficiency vs load current load current (a) 0 efficiency (%) 100 95 90 85 80 75 70 5101520 1950 f09 v in = 48v v out = 3.3v f osc = 235khz power module v out (100mv/div) lt1950 v out (100mv/div) 500 s/div 1950 f10 figure 10. output voltage transient response to load steps (0a to 3.3a) lt1950 (trace1) vs power module (trace 2) 94% efficient 3.3v, 20a synchronous forward converter the synchronous forward converter in figure 11 is based on the lt1950 and uses mosfets as synchronous output rectifiers to provide an efficient 3.3v, 20a isolated output from 48v input. the output rectifiers are driven by the ltc1698 which also serves as an error amplifier and optocoupler driver. efficiency and transient response are shown in figures 9 and 10. peak efficiencies of 94% and ultra-fast transient response are superior to presently available power modules. in addition, the circuit in figure 11 is an all-ceramic capacitor solution providing low output ripple voltage and improved reliability. the lt1950-based converter can be used to replace power module converters at a much lower cost. the lt1950 solution benefits from thermal conduction of the system board resulting in higher efficiencies and lower rise in component tempera- tures. the 7mm height allows dense packaging and the circuit can be easily adjusted to provide an output voltage from 1.23v to 15v. in addition, higher currents are achiev- able by simple scaling of power components. the lt1950- based solution in figure 11 is a powerful topology for replacement of a wide range of power modules.
lt1950 16 1950fa figure 11. 36v to 72v input to 3.3v at 20a synchronous forward converter comp fb r osc sync slope v ref shdn gnd v sec v in boost pgnd gate v in2 i sense blank lt1950 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v dd cg pgnd gnd opto v comp marg v fb =1.233v fg sync v aux i comp +i sns Ci sns p wt ok ovp ltc1698 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r4, 18k r17, 210k r1 4.7k c1 0.1 f c3 10nf +v in +v in +v in Cv in comp uv c u1 1 f r18 27k c s 10v bias 10v bias 10v bias comp u4 hcpl-m453 0.1 f c6 4.7 f d3 bat760 r2 4.7k 100k 100k r3 4.7k uv 10v bias q4 bc847bf 6 5 4 1 2 3 sync fg cg 7v bias +v 01 r14 1.2k r16 2.8k r15 4.7k c9, 33nf 1 f x5r r13 270 ? 0.1 f r9 470k 8 7 2 1 6 5 4 3 u2a ltc1693-1 u2b ltc1693-1 t1 stg-0313w q2 si7380 2 q1 si4490 fg q3 si7380 2 cg l1 c.pi-1365-1r2 c 01 100 f x5r 4 +v 01 3.3v 20a sync 220pf 560 ? t2 r7 255 ? d1 bas516 c s r s 0.015 ? c4 1000pf 47 ? d2 bat760 c in 2.2 f 100v x5r 36v to 72v input r6 18k r5 470k applicatio s i for atio wu uu
lt1950 17 1950fa slope v ref r osc blank sync fb comp v in v in2 v sec shdn gate i sense gnd pgnd lt1950 5 6 3 9 4 2 1 15 11 16 7 12 10 8 13 210k 27k 6.8k 0.1 f +v in +v in Cv in t1 pa0581 +v out c in 2.2 f 100v x5r 36v to 72v input 10v bias 470k 18k 232k 24.9k 47 f si7450 + C 330r 470pf 18k 1 f 1 f 47k 4 3 5 2 1 8.2v 22k u2 lt1009 u3 lt1797 fmmt625 oc1 1950 f13 47 h 0.015 mbr20200ct figure 13. 36v to 72v input to 26v at 5a nonsynchronous forward converter load current (a) 1 efficiency (%) 5 1950 f12 2 3 4 94 93 92 91 90 89 88 87 86 85 84 v in = 48v v out = 26v f osc = 235khz figure 12. lt1950-based nonsynchronous forward converter efficiency vs load current (figure 13 circuit) high efficiency, isolated 26v 5a output, nonsynchronous forward converter figure 13 illustrates a nonsynchronous forward converter based on the lt1950 to provide a highly efficient, 26v 5a isolated output from 48v input. the lt1950-based con- verter using a single switch topology and utilizing the lt1950s adaptive maximum duty cycle clamp is a simple and highly optimized solution. peak efficiencies of 92.8% (figure 12) are achievable. transformer and inductor are standard components. the quarter brick sized dc/dc converter (2.3" by 1.45") delivers over 125w and is only 0.4" high. the 26v converter can be used as a front line (isolating) converter in telecom systems with multiple outputs. applicatio s i for atio wu uu
lt1950 18 1950fa applicatio s i for atio wu uu figure 14. 4v to 36v input, 12v/1.5a automotive sepic converter comp fb r osc sync slope v ref shdn gnd v sec v in boost pgnd gate v in2 i sense blank lt1950 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r4 133k r10 0.010 ? r3 18k r5 16.2k r7 71.5k c1 2200pf c5 10 f 50v v in v in 4v to 36v +v out c in 10 f 50v tdk c out 47 f, 16v x5r, tdk 4 +v out 12v, 1.5a c2 0.1 f c6 0.01 f c3 4.7 f 16v c4 4.7 f 16v r8 47k r9, 47 ? r6 35.7k r1 10.5k r2 1.21k 3.3v bias q1 si7456 d2 bas516 l1 4.7 h l2* l3* d1 mbrd660ct *l2, l3 (coupled inductors) vp5-0155
lt1950 19 1950fa package descriptio u gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0502 12 3 4 5 6 7 8 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 15 14 13 .189 C .196* (4.801 C 4.978) 12 11 10 9 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) 45 0 C 8 typ .007 C .0098 (0.178 C 0.249) .053 C .068 (1.351 C 1.727) .008 C .012 (0.203 C 0.305) .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 C .165 .0250 typ .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
lt1950 20 1950fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2003 lt/tp 0504 1k rev a ? printed in usa related parts part number description comments lt1534 ultralow noise 2a switching regulator reduces conducted and radiated emi, low switching harmonics, 20khz to 250khz switching frequency lt1619 low voltage current mode controller 1.9v v in 18v, 300khz operation, boost, flyback, sepic lt1681/lt3781 dual transistor synchronous forward controller operation up to 72v maximum ltc1693 high speed mosfet driver 1.5a peak output current, 16ns rise/fall time at v cc = 12v, c l = 1nf ltc1698 secondary synchronous rectifier controller use with the lt1950 or lt1681, isolated power supplies, contains voltage margining, optocoupler driver, synchronization circuit with the primary side lt1725 general purpose isolated flyback controller no optoisolator required, accurate regulation without user trims, 50khz to 250khz switching frequency, ssop-16 package ltc1871 wide input range, no r sense tm controller operation as low as 2.5v input, boost, flyback, sepic lt1910 protected high side mosfet driver 8v to 48v supply range, protected C15v to 60v supply transient ltc3440 micropower buck-boost dc/dc converter synchronous, single inductor, no schottky diode required ltc3704 positive-to-negative dc/dc controller 2.5v v in 36v, no r sense current mode operation, excellent transient response no r sense is a trademark of linear technology corporation.

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